US 12,217,151 B2
Layout parasitics and device parameter prediction using graph neural networks
Haoxing Ren, Austin, TX (US); George Ferenc Kokai, Roseville, CA (US); Ting Ku, San Jose, CA (US); and Walker Joseph Turner, Jacksonville, FL (US)
Assigned to NVIDIA Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Apr. 3, 2023, as Appl. No. 18/295,145.
Application 18/295,145 is a continuation of application No. 16/859,585, filed on Apr. 27, 2020, granted, now 11,651,194.
Claims priority of provisional application 62/941,391, filed on Nov. 27, 2019.
Prior Publication US 2023/0237313 A1, Jul. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 16/901 (2019.01); G06F 17/16 (2006.01); G06F 30/398 (2020.01); G06N 3/04 (2023.01); G06N 3/045 (2023.01); G06N 3/082 (2023.01)
CPC G06N 3/045 (2023.01) [G06F 16/9024 (2019.01); G06F 17/16 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
at least one graph neural network;
graph generation logic configured to transform a circuit netlist into a graph; and embedding logic configured to generate a node embedding for the graph in the at least one graph neural network, the node embedding formed by concatenating previously generated node embeddings with aggregated neighbor embeddings, the node embedding configured with different edge types of the graph grouped independently for processing by different attention layers of the at least one graph neural network, wherein the at least one graph neural network is configured to transform edges of the graph into parasitic resistance predictions for the circuit netlist.