US 12,217,129 B2
Integrating circuit elements in a stacked quantum computing device
Julian Shaw Kelly, Santa Barbara, CA (US); and Joshua Yousouf Mutus, Santa Barbara, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Sep. 2, 2022, as Appl. No. 17/902,695.
Application 17/902,695 is a division of application No. 16/493,400, granted, now 11,436,516, previously published as PCT/US2017/066574, filed on Dec. 15, 2017.
Claims priority of provisional application 62/470,694, filed on Mar. 13, 2017.
Prior Publication US 2023/0004847 A1, Jan. 5, 2023
Int. Cl. G06N 10/00 (2022.01); H01L 25/065 (2023.01); H10N 60/20 (2023.01)
CPC G06N 10/00 (2019.01) [H01L 25/0657 (2013.01); H10N 60/20 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method of bonding a first chip to a second chip, the method comprising:
providing the first chip, wherein the first chip comprises a first dielectric substrate and a qubit device on the first dielectric substrate, wherein the qubit device comprises a first superconductor layer;
providing the second chip, wherein the second chip comprises a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate and separate from the qubit readout element, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer;
aligning the first chip to the second chip such that
a portion of the control wire overlaps a first portion of the first superconductor layer the qubit,
the qubit readout element overlaps a second portion of the first superconductor layer of the qubit device,
and the shielding layer is arranged between the portion of the control wire and the portion of the first superconductor layer of the qubit device to reduce crosstalk between the control wire and the qubit device; and
bonding the first chip to the second chip.