US 12,217,101 B2
Methods and apparatus to configure heterogenous components in an accelerator
Michael Behar, Zichron Yaakov (IL); Moshe Maor, Kiryat Mozking (IL); Ronen Gabbai, Ramat Hashofet (IL); Roni Rosner, Binyamina (IL); Zigi Walter, Haifa (IL); and Oren Agam, Zichron Yaacov (IL)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Apr. 28, 2023, as Appl. No. 18/309,650.
Application 18/309,650 is a continuation of application No. 16/541,979, filed on Aug. 15, 2019, granted, now 11,675,630.
Prior Publication US 2023/0333913 A1, Oct. 19, 2023
Int. Cl. G06F 9/50 (2006.01); G06F 16/901 (2019.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01)
CPC G06F 9/5083 (2013.01) [G06F 16/9024 (2019.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a communication fabric;
machine readable instructions;
a secondary memory associated with a secondary programmable circuitry, the secondary programmable circuitry in communication with primary programmable circuitry, the primary programmable circuitry associated with a primary memory;
the secondary programmable circuitry to at least one of instantiate or execute the machine readable instructions to:
receive, via the communication fabric, a first workload from the primary programmable circuitry;
allocate, via the communication fabric, a first memory portion to the first workload, the first memory portion located in either the primary memory or the secondary memory;
receive, via the communication fabric, a second workload from the primary programmable circuitry; and
allocate, via the communication fabric, a second memory portion to the second workload, the second memory portion located in either the primary memory or the secondary memory, the location of the second memory portion based on a relationship between the first workload and the second workload.