US 12,217,093 B2
Hardware acceleration for function processing
Prateek Tandon, Issaquah, WA (US); and Brian Jacob Corell, Sammamish, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jan. 4, 2024, as Appl. No. 18/404,715.
Application 18/404,715 is a division of application No. 17/586,434, filed on Jan. 27, 2022, granted, now 11,900,165.
Application 17/586,434 is a division of application No. 16/555,927, filed on Aug. 29, 2019, granted, now 11,237,873, issued on Feb. 1, 2022.
Prior Publication US 2024/0143401 A1, May 2, 2024
Int. Cl. G06F 9/46 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 13/362 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 9/3836 (2013.01); G06F 9/4843 (2013.01); G06F 13/3625 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method, comprising:
receiving a first request to execute a first function from a first set of functions;
analyzing first historical information related to a first plurality of requests received by a function processing service;
based on analyzing the first historical information, configuring a set of hardware circuits to perform the first set of functions;
receiving a second request to execute a second function from a second set of functions;
analyzing second historical information related to a second plurality of requests received by the function processing service; and
based on analyzing the second historical information configuring the set of hardware circuits to perform the second set of functions, wherein the second set of functions is different from the first set of functions.