US 12,217,060 B1
Instruction fusion
Francesco Spadini, Sunset Valley, TX (US); Skanda K. Srinivasa, Austin, TX (US); Reena Panda, Cedar Park, TX (US); Brian T. Mokrzycki, Portland, OR (US); Haoyan Jia, Ellicott City, MD (US); and Zhaoxiang Jin, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 28, 2023, as Appl. No. 18/176,457.
Claims priority of provisional application 63/376,822, filed on Sep. 23, 2022.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30181 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A processor, comprising:
fusion detector circuitry configured to:
receive fetched instructions;
detect a first pair of the fetched instructions, wherein the first pair includes:
a first instruction that is executable to:
perform a divide operation using a dividend from a first source register and a divisor from a second source register; and
write a quotient of the divide operation to a first destination register; and
a second instruction that is executable to:
read the quotient, the dividend and the divisor from the first destination register, the first source register and the second source register;
calculate a remainder of the divide operation; and
write the remainder to the first destination register, overwriting the quotient; and
fuse the first pair of the fetched instructions into a first fused instruction operation that is executable to use the dividend and the divisor to calculate the remainder and write the remainder instead of the quotient to the first destination register; and
execution circuitry coupled to the fusion detector circuitry and configured to execute the first fused instruction operation.