US 12,217,055 B2
Method and device for variable precision computing
Riccardo Alidori, Grenoble (FR); and Andrea Bocco, Grenoble (FR)
Assigned to Commissariat à l'Energie Atomique et aux Energies Alternatives, Paris (FR)
Filed by Commissariat à l'Energie Atomique et aux Energies Alternatives, Paris (FR)
Filed on Jun. 7, 2023, as Appl. No. 18/330,508.
Claims priority of application No. 2205595 (FR), filed on Jun. 10, 2022.
Prior Publication US 2023/0401059 A1, Dec. 14, 2023
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30025 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30101 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A floating-point computation circuit comprising:
an internal memory storing one or more floating-point values in a first format;
status registers defining a plurality of floating-point number format types associated with corresponding identifiers, each format type indicating at least a maximum size; and
a load and store unit for loading floating-point values from an external memory to the internal memory and storing floating-point values from the internal memory to the external memory, the load and store unit being configured:
to receive, in relation with a first store operation, a first floating-point value from the internal memory and a first of said identifiers; and
to convert the first floating-point value from the first format to a first external memory format having a maximum size defined by the floating-point number format type designated by the first identifier.