| CPC G06F 9/30018 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30105 (2013.01); G06F 9/3895 (2013.01)] | 18 Claims |
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1. A method comprising:
receiving a processor instruction for a first processor that specifies a portion of a first vector stored in a first source register of the first processor, a portion of a second vector stored in a second source register of the first processor, and a first destination register;
generating a predication instruction to mask one or more lanes of each of a third source register and a fourth source register of a second processor, in which the third and fourth source registers store the first and second vectors, respectively, and in which each of the third and fourth source registers is larger than each of the first and second source registers; and
based on a translation of the processor instruction for execution by a second processor:
reading the portion of the first vector from unmasked lanes of the third source register;
reading the portion of the second vector from unmasked lanes of the fourth source register;
interleaving the portion of the first vector read from the unmasked lanes of the third source register with the portion of the second vector read from the unmasked lanes of the fourth source register to produce a third vector; and
storing the third vector in a second destination register of the second processor.
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