US 12,217,021 B2
Processing unit with small footprint arithmetic logic unit
Bin He, Orlando, FL (US); Shubh Shah, Santa Clara, CA (US); and Michael Mantor, Orlando, FL (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Jul. 7, 2023, as Appl. No. 18/219,268.
Application 18/219,268 is a continuation of application No. 17/029,836, filed on Sep. 23, 2020, granted, now 11,720,328.
Claims priority of provisional application 63/044,544, filed on Jun. 26, 2020.
Prior Publication US 2024/0143283 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/57 (2006.01); G06F 17/16 (2006.01); G06N 3/08 (2023.01)
CPC G06F 7/57 (2013.01) [G06F 17/16 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
executing a plurality of mathematical operations with a plurality of operands using an arithmetic logic unit (ALU); and
reducing a first operand and a second operand of the plurality of operands by discarding at least a portion of each of the first operand and the second operand, wherein the discarded portion of the first operand and the discarded portion of the second operand include different numbers of bits.