US 12,217,019 B2
Processing-in-memory devices having multiplication-and-accumulation circuits
Choung Ki Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 26, 2021, as Appl. No. 17/331,426.
Application 17/331,426 is a continuation of application No. 17/319,717, filed on May 13, 2021.
Claims priority of application No. 10-2021-0003632 (KR), filed on Jan. 11, 2021.
Prior Publication US 2022/0222045 A1, Jul. 14, 2022
Int. Cl. G06F 7/544 (2006.01); G06F 7/487 (2006.01); G06F 7/501 (2006.01); G11C 7/10 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 7/4876 (2013.01); G06F 7/501 (2013.01); G11C 7/1012 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A processing-in-memory (PIM) device comprising:
a first memory bank configured to store weight data comprised of elements of a weight matrix;
a second memory bank configured to store vector data comprised of elements of a vector matrix;
a buffer configured to store constant data; and
a multiplication-and-accumulation (MAC) circuit configured to selectively perform at least one of: a MAC arithmetic operation of the weight data and the vector data, and an element-wise multiplication (EWM) arithmetic operation of the weight data and the constant data,
wherein the MAC circuit comprising:
a MAC operator circuit configured to selectively perform the MAC arithmetic operation or the EWM arithmetic operation; and
a data input circuit configured to provide the MAC operator circuit with the weight data, the vector data, and the constant data,
wherein the data input circuit comprising:
a first input latch configured to latch the weight data and output latched weight data to the MAC operator circuit;
a data selection circuit configured to receive the vector data and the constant data to selectively output the vector data or the constant data according to the selected arithmetic operation; and
a second input latch configured to latch output data of the data selection circuit and output latched output data to the MAC operator circuit, and
wherein the data selection circuit includes:
a third input latch configured to latch and output the constant data;
a bit copy block configured to copy the constant data outputted from the third input latch to generate and output replica constant data; and
a data selection output circuit configured to selectively output the replica constant data or the vector data.