US 12,217,018 B2
Method and architecture for performing modular addition and multiplication sequences
Brian C. Koziel, Plano, TX (US); and Rami El Khatib, Boca Raton, FL (US)
Assigned to PQSecure Technologies, LLC, Boca Raton, FL (US)
Appl. No. 17/925,367
Filed by PQSecure Technologies, LLC, Boca Raton, FL (US)
PCT Filed Sep. 20, 2021, PCT No. PCT/US2021/051136
§ 371(c)(1), (2) Date Mar. 23, 2023,
PCT Pub. No. WO2023/043467, PCT Pub. Date Mar. 23, 2023.
Prior Publication US 2024/0220201 A1, Jul. 4, 2024
Int. Cl. G06F 7/523 (2006.01); G06F 7/50 (2006.01)
CPC G06F 7/523 (2013.01) [G06F 7/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer processing system comprising:
at least one arithmetic logic unit in a computer processing device operably configured to perform quadratic extension field multiplication for use in an isogeny-based cryptosystem and having:
at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum; and
at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation as part of the quadratic extension field multiplication and generate a modular multiplication operation result without a conditional subtraction circuit in the at least one arithmetic logic unit.