US 12,217,002 B2
Parallel processing of hierarchical text
Elias Stehle, Pfäffikon (CH); and Gregory Michael Kimball, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on May 11, 2022, as Appl. No. 17/742,150.
Prior Publication US 2023/0367964 A1, Nov. 16, 2023
Int. Cl. G06F 17/00 (2019.01); G06F 40/14 (2020.01); G06F 40/149 (2020.01); G06F 40/284 (2020.01)
CPC G06F 40/284 (2020.01) [G06F 40/14 (2020.01); G06F 40/149 (2020.01)] 23 Claims
OG exemplary drawing
 
1. A processor, comprising:
a plurality of processing units to perform one or more operations from a list of operations comprising:
grouping one or more sequences of an input stream into one or more tokens based, at least in part, on simulating a finite state transducer;
identifying, using at least one logical stack, one or more hierarchical relationships between the one or more tokens;
generating a data tree based, at least in part, on the identified one or more hierarchical relationships; and
analyzing the data tree in parallel to identify one or more shared paths of one or more nodes in the data tree, infer schema information from the one or more shared paths, and store data from the input stream in accordance with the schema information.