US 12,216,978 B2
Routing structure of semiconductor device and forming method thereof
Anurag Verma, Hsinchu (TW); Meng-Kai Hsu, Hsinchu County (TW); Chih-Wei Chang, Hsinchu (TW); Sang-Chi Huang, Hsinchu (TW); Wei-Ling Chang, Hsinchu (TW); and Hui-Zhong Zhuang, Kaohsiung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Apr. 8, 2021, as Appl. No. 17/225,903.
Prior Publication US 2022/0327277 A1, Oct. 13, 2022
Int. Cl. G06F 30/3953 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC G06F 30/3953 (2020.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/088 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/41733 (2013.01); H01L 29/41775 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A layout method, executed by at least one processor, comprising:
determining a number M of tracks in a first direction for a cell, wherein M is a natural number;
generating a design layout by placing the cell, wherein the cell comprises:
a transistor disposed in a transistor layer having a gate electrode extending in the first direction;
a first power rail and a second power rail extending in a second direction perpendicular to the first direction in a first layer over the transistor layer, wherein the first power rail and the second power rail are disposed on opposite sides of the cell; and
a plurality of first conductive segments extending in the second direction between the first and second power rails in the first layer, wherein the first conductive segments are configured as input/output pins of the cell;
receiving a design rule check (DRC) deck, the DRC deck containing a minimal segment end spacing;
providing a third power rail extending in the first direction in a second layer over the first layer, the third power rail occupying one of the M tracks in the cell; and
in response to the occupied one of the M tracks, providing M second conductive segments extending in the first direction in the second layer, wherein each of the M second conductive segments is aligned with one of remaining M-1 tracks and configured to be electrically connected to one of the first conductive segments,
wherein at least two of the M second conductive segments are all aligned with a single track of the remaining M-1 tracks in the first direction and are separated by a spacing substantially equal to or greater than the minimal segment end spacing.