US 12,216,976 B2
Efficient integrated circuit simulation and testing
Evelyn Landman, Haifa (IL); Yair Talker, Binyamina (IL); Eyal Fayneh, Givatayim (IL); Yahel David, Kibbutz Gazit (IL); Shai Cohen, Haifa (IL); and Inbar Weintrob, Givat-Ada (IL)
Assigned to PROTEANTECS LTD., Haifa (IL)
Filed by PROTEANTECS LTD., Haifa (IL)
Filed on Sep. 24, 2021, as Appl. No. 17/485,168.
Application 17/485,168 is a continuation of application No. 17/254,468, granted, now 11,132,485, previously published as PCT/IL2019/050686, filed on Jun. 19, 2019.
Claims priority of provisional application 62/686,744, filed on Jun. 19, 2018.
Prior Publication US 2022/0012395 A1, Jan. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); G06F 30/3312 (2020.01); G06F 111/08 (2020.01); G06F 119/06 (2020.01); G06F 119/22 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 2111/08 (2020.01); G06F 2119/06 (2020.01); G06F 2119/22 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising using at least one hardware processor for:
running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types;
based on results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations;
receiving an IC design embodied as a digital file;
correlating the received IC design with the library; and
based on said correlating, predicting at least one of:
a frequency distribution, or
a power distribution,
of ICs manufactured according to the IC design.