CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 15 Claims |
1. A memory controller comprising:
a first interface configured to communicate with an external device;
a second interface configured to communicate with a memory;
a command queue configured to store commands received from the external device; and
a processor configured to perform a control operation according to a command stored in the command queue, and suspend the performance of the control operation according to the command for a waiting time corresponding to a value of a mutex counter for the command, when a mutex flag for the command is activated.
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