US 12,216,932 B2
Precise longitudinal monitoring of memory operations
Ahmad Yasin, Haifa (IL); Michael Chynoweth, Placitas, NM (US); Rajshree Chabukswar, Sunnyvale, CA (US); and Muhammad Taher, Umm El Fahm (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 1, 2023, as Appl. No. 18/327,474.
Application 18/327,474 is a continuation of application No. 15/929,272, filed on Apr. 21, 2020, granted, now 11,693,588.
Application 15/929,272 is a continuation of application No. 16/177,642, filed on Nov. 1, 2018, granted, now 10,649,688, issued on May 12, 2020.
Prior Publication US 2023/0305742 A1, Sep. 28, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 11/34 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G06F 11/3466 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory subsystem including a data cache, the memory subsystem to process a load operation; and
load latency hardware including a latency counter, the load latency hardware to record performance monitoring information including an access address associated with the load operation, a data block indicator to indicate whether the load operation was blocked since its data could not be forwarded from a preceding store, and an address block indicator to indicate whether the load operation was blocked due to a potential address conflict with a preceding store.