US 12,216,923 B2
Computer system, memory expansion device and method for use in computer system
Yijin Guan, Beijing (CN); Tianchan Guan, Shanghai (CN); Dimin Niu, San Mateo, CA (US); and Hongzhong Zheng, Los Gatos, CA (US)
Assigned to ALIBABA (CHINA) CO., LTD., Zhejiang Province (CN)
Filed by ALIBABA (CHINA) CO., LTD., Zhejiang Province (CN)
Filed on Dec. 12, 2022, as Appl. No. 18/064,500.
Claims priority of application No. 202211059501.8 (CN), filed on Aug. 31, 2022.
Prior Publication US 2024/0069755 A1, Feb. 29, 2024
Int. Cl. G06F 13/00 (2006.01); G06F 1/16 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0622 (2013.01) [G06F 1/1632 (2013.01); G06F 3/0607 (2013.01); G06F 3/0632 (2013.01); G06F 3/0683 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A computer system, comprising:
a plurality of hosts, wherein each host comprises:
a CPU; and
a memory; and
a plurality of memory expansion devices, wherein the plurality of memory expansion devices correspond to the plurality of hosts in a one-to-one manner, wherein each memory expansion device comprises:
a first interface, configured to allow each memory expansion device to communicate with the corresponding CPU via a first coherence interconnection protocol; and
a plurality of second interfaces, configured to allow each memory expansion device to communicate with a portion of memory expansion devices of the plurality of memory expansion devices via a second coherence interconnection protocol;
wherein any two memory expansion devices of the plurality of memory expansion devices communicate with each other via at least two different paths, and the number of memory expansion devices that at least one of the two paths passes through is not more than one, and
wherein the CPU of a first host of the plurality of hosts is capable of accessing the memory of a second host of the plurality of hosts via the interconnected memory expansion devices that are operatively interconnected by the second coherence interconnection protocol.