US 12,216,922 B2
Updating encrypted security context in stack pointers for exception handling and tight bounding of on-stack arguments
Hans G. Liljestrand, Raasepori (FI); Sergej Deutsch, Hillsboro, OR (US); David M. Durham, Beaverton, OR (US); Michael LeMay, Hillsboro, OR (US); and Karanvir S. Grewal, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 16, 2022, as Appl. No. 17/947,072.
Prior Publication US 2023/0018585 A1, Jan. 19, 2023
Int. Cl. G06F 3/06 (2006.01); H04L 9/32 (2006.01)
CPC G06F 3/0622 (2013.01) [G06F 3/0638 (2013.01); G06F 3/0655 (2013.01); H04L 9/32 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor to be coupled to a memory to store code, the processor to:
execute a first instruction to perform a first simulated return in a program from a callee function to a caller function based on a first input stack pointer encoded with a first security context of a callee stack frame, wherein the first simulated return is to simulate a normal return from the callee function that is cryptographically protected, wherein to perform the first simulated return is to include:
generating a first simulated stack pointer to a caller stack frame; and
in response to identifying an exception handler in the caller function, execute a second instruction to perform a simulated call based on a second input stack pointer encoded with a second security context of the caller stack frame, wherein the simulated call is to simulate a normal call from the caller function that is cryptographically protected, wherein to perform the simulated call is to include:
generating a second simulated stack pointer to a new stack frame containing an encrypted instruction pointer associated with the exception handler, the second simulated stack pointer to be encoded with a new security context of the new stack frame.