US 12,216,914 B2
Apparatus and method for power-loss data protection in a system
Jin Pyo Kim, Gyeonggi-do (KR); Ju Hyun Kim, Gyeonggi-do (KR); Jong Soon Park, Gyeonggi-do (KR); Woong Sik Shin, Gyeonggi-do (KR); and Woo Young Yang, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 3, 2022, as Appl. No. 17/958,498.
Claims priority of application No. 10-2022-0046949 (KR), filed on Apr. 15, 2022.
Prior Publication US 2023/0333750 A1, Oct. 19, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0253 (2013.01); G06F 2212/1032 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory device including a first memory block used for power-loss data protection; and
a controller coupled to the memory device, the controller including a hardware layer and a firmware layer, the hardware layer configured to:
check whether at least one write data entry input from an external device to be programmed in the memory device belongs to a programmable range in the memory device after power loss occurs,
determine whether a logical address associated with the at least one write data entry is repeated, and
program the at least one write data entry in the first memory block after the checking and the determining, wherein:
the firmware layer is configured to process a write data entry for a program operation, and
the controller is configured to set an identifier to the write data entry completely processed by the firmware layer.