US 12,216,909 B2
Memory module and memory system including row hammer counter chip and operating method thereof
Taekwoon Kim, Suwon-si (KR); and Youngsoo Sohn, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 22, 2022, as Appl. No. 17/992,516.
Claims priority of application No. 10-2021-0188869 (KR), filed on Dec. 27, 2021.
Prior Publication US 2023/0205428 A1, Jun. 29, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory module comprising:
a plurality of data chips each of which is configured to store a data set corresponding to a plurality of burst lengths; and
at least one row hammer counter chip comprising a plurality of counter memory cells, each of the plurality of counter memory cells connected to a word line, among a plurality of word lines, for each of the plurality of data chips,
wherein the at least one row hammer counter chip is configured to independently store in each of the plurality of counter memory cells connected to the word line, a number of times the word line is accessed for each of the plurality of data chips during a row hammer monitoring time frame,
wherein the plurality of counter memory cells comprises:
a plurality of first word line cells connected to a first word line, among the plurality of word lines, and
a plurality of second word line cells connected to a second word line, among the plurality of word lines, and
wherein the plurality of first word line cells comprises:
a plurality of first data chip cells dedicated for storing a number of times a first word line of a first data chip, among the plurality of data chips, is accessed, and
a plurality of second data chip cells dedicated for storing a number of times a first word line of a second data chip, among the plurality of data chips, is accessed.