US 12,216,906 B2
Host techniques for stacked memory systems
Joseph T. Pawlowski, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 11, 2022, as Appl. No. 17/942,163.
Application 17/942,163 is a continuation of application No. 17/127,707, filed on Dec. 18, 2020, granted, now 11,455,098.
Claims priority of provisional application 62/953,825, filed on Dec. 26, 2019.
Prior Publication US 2023/0004305 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/067 (2013.01); G06F 3/0688 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
a storage device including a first memory device of a first type of volatile memory and a second memory device of a second type of volatile memory;
a host device coupled to the storage device, the host device configured to issue commands to the storage device to store and retrieve information of the system; and
a logic die comprising:
an interface circuit configured to receive the commands from the host device using an external bus; and
a controller configured to control data communication between the interface circuit and the first memory device, wherein the second memory device is configured as an exclusive data target for exchanging data between the storage device and the host device, and wherein each respective data exchange, using the external bus between the storage device and the host device, includes data passed via the second memory device.