US 12,216,866 B2
Fingerprint sensor and display device including the same
Ji Sun Kim, Yongin-si (KR); and Mu Kyung Jeon, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Apr. 17, 2023, as Appl. No. 18/301,974.
Application 18/301,974 is a continuation of application No. 16/162,050, filed on Oct. 16, 2018, granted, now 11,631,271.
Claims priority of application No. 10-2017-0154128 (KR), filed on Nov. 17, 2017.
Prior Publication US 2023/0251747 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/044 (2006.01); G06F 3/041 (2006.01); G06V 10/147 (2022.01); G06V 40/13 (2022.01)
CPC G06F 3/044 (2013.01) [G06F 3/0416 (2013.01); G06V 10/147 (2022.01); G06V 40/1306 (2022.01); G06F 2203/04112 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A fingerprint sensor comprising:
at least one sensor pixel arranged in a sensing area,
wherein the sensor pixel includes:
a pixel electrode coupled to a first node;
a first transistor including a source electrode and a drain electrode, the first transistor being coupled between the first node and a first power line, the first transistor including a first gate electrode coupled to a first scan line and a second gate electrode opposite to the first gate electrode, the second gate electrode being coupled to the first power line;
a first capacitor coupled between the first node and a second scan line, and comprising a first electrode and a second electrode, the second electrode comprising a portion of the pixel electrode;
a second transistor coupled between a readout line and a second power line, the second transistor including a first gate electrode coupled to the first node and a second gate electrode opposite to the first gate electrode; and
a third transistor coupled between the second transistor and the second power line, the third transistor including a first gate electrode coupled to the second scan line and a second gate electrode opposite to the first gate electrode,
wherein the source electrode of the first transistor is electrically connected to the second gate electrode of the first transistor and the first power line,
wherein the drain electrode of the first transistor is electrically connected to the pixel electrode and the second electrode of the first capacitor,
wherein the first transistor is electrically coupled between the first power line and the pixel electrode along a first current path, and the second transistor is electrically coupled between the readout line and the second power line along a second current path separate from the first current path, and
wherein the drain electrode of the first transistor is electrically coupled between the pixel electrode and the source electrode of the first transistor.