US 12,216,770 B2
Signal processing device and signal processing method
Tatsuya Kaneko, Kanagawa (JP); and Yuichi Motohashi, Tokyo (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Filed on Nov. 14, 2022, as Appl. No. 17/986,114.
Application 17/986,114 is a continuation of application No. 17/718,628, filed on Apr. 12, 2022, granted, now 11,868,487.
Application 17/718,628 is a continuation of application No. 16/620,086, granted, now 11,361,085, issued on Jun. 14, 2022, previously published as PCT/JP2018/021143, filed on Jun. 1, 2018.
Claims priority of application No. 2017-118494 (JP), filed on Jun. 16, 2017.
Prior Publication US 2023/0071178 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/60 (2013.01); G06V 20/56 (2022.01); H04L 9/40 (2022.01)
CPC G06F 21/602 (2013.01) [G06V 20/56 (2022.01); H04L 63/0428 (2013.01); H04L 63/083 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An imaging device, comprising:
a plurality of pixels configured to generate a signal of an image data;
an encryption processing unit configured to output encrypted data based on a portion of the image data; and
an image output unit configured to output one frame of the image data and the encrypted data in a format, wherein
the format includes:
a frame start region,
a packet header region,
a first region for the one frame of the image data,
a second region for the encrypted data,
a packet footer region, and
a frame end region,
the first region is between the packet header region and the packet footer region, and
the second region is between the packet header region and the packet footer region.