US 12,216,735 B2
Supporting floating point 16 (FP16) in dot product architecture
Hamzah Ahmed Ali Abdelaziz, San Jose, CA (US); Ali Shafiee Ardestani, San Jose, CA (US); and Joseph H. Hassoun, Los Gatos, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 20, 2021, as Appl. No. 17/153,871.
Claims priority of provisional application 63/008,544, filed on Apr. 10, 2020.
Prior Publication US 2021/0319079 A1, Oct. 14, 2021
Int. Cl. G06F 17/16 (2006.01); G06F 7/544 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 7/5443 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device for calculating dot-products of a first vector and a second vector, the device comprising:
an array of multiplier units of a processor of the device, a multiplier unit of the array of multiplier units to:
determine a product-integer value based on integer values of corresponding elements of the first vector and the second vector, the first vector and the second vector comprising floating-point values;
determine an unbiased exponent value corresponding to the product-integer value based on exponent values corresponding to the integer values of the corresponding elements of the two vectors, wherein:
the multiplier unit of the array of multiplier units includes a local shifter that forms a first shifted value by shifting the product-integer value by a number of bits in a predetermined direction based on a difference value between the unbiased exponent value corresponding to the product-integer value and a maximum unbiased exponent value for the array of multiplier units being less than or equal to a predetermined maximum bit-shift capacity of the local shifter, and
the processor determines the maximum unbiased exponent value for the array of multiplier units;
an adder tree that adds first shifted values output from local shifters of the array of multiplier units to form a first output;
an auxiliary shifter coupled to the adder tree and that forms a second shifted value by shifting a second output from the adder tree by the predetermined maximum bit-shift capacity of the local shifter; and
an accumulator that accumulates the first output of the adder tree, wherein the processor provides an inference of a deep neural network model based at least in part on the accumulator accumulating the first output of the adder tree.