US 12,216,734 B2
Apparatus and method for conjugate transpose and multiply
Menachem Adelman, Haifa (IL); Robert Valentine, Kiryat Tivon (IL); Daniel Towner, Bath (GB); Amit Gradstein, Binyamina (IL); and Mark Jay Charney, Lexington, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/133,456.
Prior Publication US 2022/0197975 A1, Jun. 23, 2022
Int. Cl. G06F 17/16 (2006.01); G06F 7/523 (2006.01); G06F 7/78 (2006.01); G06F 9/30 (2018.01)
CPC G06F 17/16 (2013.01) [G06F 7/523 (2013.01); G06F 7/78 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30145 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A processor comprising:
a decoder to decode a single complex matrix conjugation and multiplication instruction including a first source operand to identify a first complex source matrix comprising a first plurality of complex values including a corresponding first plurality of real values and a corresponding first plurality of imaginary values, a second source operand to identify a second complex source matrix comprising a second plurality of complex values including a corresponding second plurality of real values and a corresponding second plurality of imaginary values, a first destination operand to identify an imaginary result matrix, and an opcode to indicate a combined complex matrix conjugation and multiplication operation using the first plurality of complex values and the second plurality of complex values to generate the imaginary result matrix;
execution circuitry to execute the single complex matrix conjugation and multiplication instruction, the execution circuitry comprising:
matrix conjugation hardware logic comprising inversion circuitry to determine a plurality of complex conjugate values corresponding to the first plurality of complex values by inverting sign values of the corresponding first plurality of imaginary values to generate a corresponding plurality of sign-inverted imaginary values;
transpose hardware logic to transpose the plurality of complex conjugate values to generate a conjugate transpose matrix comprising the plurality of complex conjugate values including the corresponding plurality of sign-inverted imaginary values;
parallel multiplication circuitry to:
multiply real values from the plurality of complex conjugate values of the conjugate transpose matrix with corresponding imaginary values from the second plurality of complex values to generate a first plurality of imaginary products, and
multiply the sign-inverted imaginary values from the plurality of complex conjugate values of the conjugate transpose matrix with corresponding real values from the second plurality of complex values to generate a second plurality of imaginary products; and
addition/subtraction circuitry to add each imaginary product in the first plurality of imaginary products to a corresponding imaginary product in the second plurality of imaginary products to produce a corresponding imaginary value of the imaginary result matrix.