US 12,216,611 B2
Artificial intelligence chip and artificial intelligence chip-based data processing method
Kuen Hung Tsoi, Guangdong (CN); and Xinyu Niu, Guangdong (CN)
Assigned to Shenzhen Corerain Technologies Co., Ltd., Shenzhen (CN)
Filed by Shenzhen Corerain Technologies Co., Ltd., Guangdong (CN)
Filed on Dec. 20, 2022, as Appl. No. 18/069,216.
Application 18/069,216 is a continuation in part of application No. PCT/CN2021/101414, filed on Jun. 22, 2021.
Claims priority of application No. 202010575487.1 (CN), filed on Jun. 22, 2020.
Prior Publication US 2023/0126978 A1, Apr. 27, 2023
Int. Cl. G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 15/82 (2006.01); G06F 21/44 (2013.01)
CPC G06F 15/825 (2013.01) [G06F 21/44 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An artificial intelligence (AI) chip, comprising a data flow network for processing, on a basis of an AI algorithm, data to be processed, the data flow network comprising:
at least one calculation module, each configured to calculate, on a basis of one of at least one operation node corresponding to the AI algorithm, the data to be processed, and output a calculation result; and
a next transfer module corresponding to each calculation module, connected to each calculation module, and configured to receive the calculation result output by each calculation module and process the calculation result,
wherein the data to be processed flows in the data flow network according to a preset data flow direction;
wherein a control flow dam is disposed between each calculation module and the next transfer module, the control flow dam being configured to control a flow of the calculation result from each calculation module to the next transfer module;
wherein the control flow dam comprises a write end, a read end, a full-load end, and a no-load end, and further comprises:
a first AND gate connected to the write end to constitute an uplink valid end, the uplink valid end being configured to receive a first valid signal transmitted by each calculation module;
a second AND gate connected to the read end to constitute a downlink permission end, the downlink permission end being configured to receive a second permission signal transmitted by the next transfer module;
a first NOT gate connected to the full-load end to constitute an uplink permission end, the uplink permission end being configured to transmit a first permission signal to each calculation module and the first AND gate; and
a second NOT gate connected to the no-load end to constitute a downlink valid end, the downlink valid end being configured to transmit a second valid signal to the next transfer module and the second AND gate.