US 12,216,610 B2
Computational array microprocessor system using non-consecutive data formatting
Emil Talpes, Austin, TX (US); William McGee, Austin, TX (US); and Peter Joseph Bannon, Austin, TX (US)
Assigned to Tesla, Inc., Austin, TX (US)
Filed by Tesla, Inc., Austin, TX (US)
Filed on Jun. 15, 2023, as Appl. No. 18/335,944.
Application 18/335,944 is a continuation of application No. 17/451,984, filed on Oct. 22, 2021, granted, now 11,681,649.
Application 17/451,984 is a continuation of application No. 15/920,173, filed on Mar. 13, 2018, granted, now 11,157,441, issued on Oct. 26, 2021.
Application 15/920,173 is a continuation in part of application No. 15/710,433, filed on Sep. 20, 2017, granted, now 10,671,349, issued on Jun. 2, 2020.
Claims priority of provisional application 62/628,212, filed on Feb. 8, 2018.
Claims priority of provisional application 62/625,251, filed on Feb. 1, 2018.
Claims priority of provisional application 62/536,399, filed on Jul. 24, 2017.
Prior Publication US 2023/0409519 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/80 (2006.01); G06N 3/045 (2023.01); G06N 3/048 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01)
CPC G06F 15/8023 (2013.01) [G06N 3/045 (2023.01); G06N 3/048 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06F 2207/4824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microprocessor system, comprising:
a computational array that includes a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value of a group of values addressed from memory and a first portion of the group of values operated by the plurality of computation units are synchronously provided together to the computational array to be processed in parallel in a first computation processing; and
a hardware data formatter configured to, based on a stride, provide the first portion of the group of values to the computational array for the first computation processing and identify a second portion of the group of values not provided for the first computation processing, wherein the hardware data formatter is configured to perform a cache check to obtain the first portion of the group of values,
and wherein the second portion of the group of values are stored and provided, by the hardware data formatter, to the computational array for a second computation processing subsequent to the first computation processing.