US 12,216,607 B2
Source ordering in device interconnects
Debendra Das Sharma, Saratoga, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 22, 2021, as Appl. No. 17/238,156.
Claims priority of provisional application 63/114,440, filed on Nov. 16, 2020.
Prior Publication US 2021/0240655 A1, Aug. 5, 2021
Int. Cl. G06F 13/42 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 13/1626 (2013.01); G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 2213/0026 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a port to transmit and receive data over a link; and
protocol stack circuitry to implement one or more layers of a Peripheral Component Interconnect Express (PCIe)-based or a Compute Express Link (CXL)-based protocol across the link, wherein protocol stack circuitry is to:
receive a request to initiate a memory write transaction on the link;
construct a memory write request transaction layer packet (TLP) for the memory write transaction, wherein fields of the memory write request TLP indicate a virtual channel (VC) other than VC0 for the TLP, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction;
cause the memory write request TLP to be transmitted over the link; and
process a completion TLP received over the link, the completion TLP indicating a completion for the memory write request TLP.