US 12,216,603 B2
Reconfigurable peripheral component interconnect express (PCIe) data path transport to remote computing assets
Jitender Miglani, Hollis, NH (US); Will Ferry, Bloomsburg, PA (US); and Dileep Desai, San Jose, CA (US)
Assigned to Drut Technologies Inc., Nashua, NH (US)
Filed by Drut Technologies Inc., Nashua, NH (US)
Filed on Jan. 9, 2024, as Appl. No. 18/408,391.
Application 18/408,391 is a continuation of application No. 17/524,641, filed on Nov. 11, 2021, granted, now 11,907,151.
Prior Publication US 2024/0143534 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01); G02B 6/35 (2006.01); G06F 13/40 (2006.01)
CPC G06F 13/4027 (2013.01) [G02B 6/3518 (2013.01); G02B 6/3546 (2013.01); G06F 13/4282 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A computing system comprising:
a first fabric interface device coupled to receive first multi-lane serial peripheral component interconnect express (PCIe) data from first functional elements of a first computing asset through a first multi-lane PCIe bus, wherein the first fabric interface device is configured to transparently extend the first multi-lane PCIe bus by converting the first multi-lane PCIe data into a retimed parallel version of the first multi-lane PCIe data to be sent on a first bidirectional data communication path, wherein the first multi-lane PCIe bus has a first number of lanes and the first bidirectional data communication path has a second number of lanes; wherein the first number does not equal the second number, wherein the retimed parallels version of the first multi-lane PCIe data has a higher clock domain or frequency than the first multi-lane PCIe data; and wherein the first number of lanes is less than the second number of lanes; wherein the first bidirectional data communication path is configured to be connected through a data path transport to a second bidirectional data communication path; and
a second fabric interface device coupled to receive multi-lane serial peripheral component interconnect express (PCIe) data from second functional elements of a second computing asset through a second multi-lane PCIe bus, wherein the second fabric interface device is configured to transparently extend the second multi-lane PCIe bus by converting the second multi-lane PCIe data into a second retimed parallel version of the second multi-lane PCIe data to be sent on the second bidirectional data communication path, wherein the second multi-lane PCIe bus has a third number of lanes and the second bidirectional data communication path has a fourth number of lanes; wherein the third number does not equal the fourth number.