US 12,216,601 B2
Bus decoder
Frode Milch Pedersen, Trondheim (NO); and Markku Vähätaini, Oulu (FI)
Assigned to Nordic Semiconductor ASA, Trondheim (NO)
Filed by NORDIC SEMICONDUCTOR ASA, Trondheim (NO)
Filed on May 18, 2022, as Appl. No. 17/747,511.
Claims priority of application No. 20215598 (FI), filed on May 20, 2021.
Prior Publication US 2022/0374377 A1, Nov. 24, 2022
Int. Cl. G06F 13/362 (2006.01); G06F 11/34 (2006.01)
CPC G06F 13/362 (2013.01) [G06F 11/349 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A bus decoder, operationally connectable to a set of master units and a set of slave units, comprising circuitry configured to cause the decoder to:
receive an address from a master unit trying to access a slave unit;
map the received address to a slave address;
associate default access permissions to the master-slave connection, where a specific subset of the default access permissions is accessible to each master, the default access permissions being dependent on which slave the master is trying to access;
determine additional access permissions associated with the master unit and the slave address, where a specific subset of the additional access permissions is accessible to each master, additional access permissions being obtained from an override table and depending on which master is trying to access the slave; and
enable the master-slave connection if additional access permissions allow the master unit to access the slave, otherwise reject the connection.