US 12,216,596 B2
ZQ calibration circuit and method for memory interfaces
Mohammad Reza Mahmoodi, Goleta, CA (US); and Martin Lueker-Boden, Fremont, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Sep. 9, 2022, as Appl. No. 17/941,790.
Prior Publication US 2024/0086347 A1, Mar. 14, 2024
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1694 (2013.01) [G06F 13/1673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A termination leg unit circuit comprising:
a first circuit comprising a first plurality of switches configured to switchably connect a voltage supply to a data bus according to a target impedance between the voltage supply and the data bus; and
a second circuit connected in series between the first circuit and the data bus, the second circuit comprising a second plurality of switches configured to switchably connect a plurality of resistors between the first circuit and the data bus according to the target impedance, wherein the second circuit comprises a plurality of pairs, each pair comprising one of the second plurality of switches connected in parallel with one of the plurality of resistors.