US 12,216,594 B2
Read arbiter circuit with dual memory rank support
Shane J. Keil, San Jose, CA (US); Gregory S. Mathews, Saratoga, CA (US); and Lakshmi Narasimha Murthy Nukala, Pleasanton, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 19, 2023, as Appl. No. 18/469,905.
Claims priority of provisional application 63/376,215, filed on Sep. 19, 2022.
Prior Publication US 2024/0095194 A1, Mar. 21, 2024
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1626 (2013.01) [G06F 13/1678 (2013.01); G06F 13/1689 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory ranks including a given memory rank that includes a plurality of memory circuits coupled to a common communication bus; and
a memory control circuit configured to:
receive a plurality of read requests for the plurality of memory ranks, wherein the plurality of read requests includes a first subset of read requests to a first memory rank of the plurality of memory ranks, and a second subset of read requests to a second memory rank of the plurality of memory ranks;
in response to an initiation of a read turn to the plurality of memory ranks, allocate, based on respective numbers of requests in the first subset and the second subset, a first number of slots of a total number of slots for read requests included in the first subset, and a second number of slots of the total number of slots for read requests included in the second subset;
determine, for the read turn, a number of rank switches between the first memory rank and the second memory rank based on at least one quality-of-service requirement associated with the plurality of read requests; and
perform allocated read requests during the read turn using the number of rank switches.