| CPC G06F 13/1626 (2013.01) [G06F 13/1668 (2013.01)] | 15 Claims |
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1. A memory system comprising:
a semiconductor memory device comprising
a first circuit,
a plurality of second circuits each including a memory cell array,
a first number of first channels connected to the first circuit, each of which is connected to one or more of the plurality of second circuits, the first number being two or more; and
a control circuit connected to the semiconductor memory device via a second channel, the control circuit configured to:
generate a plurality of first access requests each for requesting a data transfer with a designation of one of the plurality of second circuits as an access target,
determine an order of execution of the plurality of first access requests to allow concurrent execution of a second number of first access requests designating as access targets two or more of the plurality of second circuits connected to different first channels of the first number of first channels, the second number being an
integer of one or more and the first number or less, and execute in parallel the second number of data transfers responsive to the second number of first access requests via the second channel at a transfer rate the second number of times a transfer rate of one of the first number of first channels, wherein
the control circuit is further configured to:
when the number of the first access requests designating the second circuits connected to the different first channels as access targets is less than the second number,
generate one or more second access requests for requesting transfer of dummy data, and
execute in parallel the second number of third access requests including one or more of the plurality of first access requests and the one or more second access requests.
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