US 12,216,590 B2
Intermediate cache management for non-uniform memory architecture
Saurabh Sharma, Santa Clara, CA (US); Hashem Hashemi, Roseville, CA (US); and Guennadi Riguer, Markham (CA)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed on Jun. 9, 2023, as Appl. No. 18/208,059.
Prior Publication US 2024/0411706 A1, Dec. 12, 2024
Int. Cl. G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/126 (2016.01)
CPC G06F 12/126 (2013.01) [G06F 12/0811 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A processing system, comprising:
a cache at a first subset of dies of the processing system; and
a cache controller configured to:
adaptively prioritize one of local data and non-local data for replacement at the cache based on a cache replacement policy and a proportion of local data to non-local data stored at the cache, wherein:
local data comprises data accessed from a local memory at the first subset of dies via a local memory channel; and
non-local data comprises data accessed from a non-local memory at a second subset of dies of the processing system via a non-local memory channel.