CPC G06F 12/10 (2013.01) | 17 Claims |
1. A memory module comprising:
J memory chips configured to input and output (input/output) data in response to each of a plurality of translated address signals; and
an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction bit values to a target address signal provided from a device external to the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that a group of K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to a different position of each bit string,
wherein J represents a number greater than 2, and
wherein K represents a number greater than 2.
|