US 12,216,587 B2
Packet cache system and method
Jiazhen Zheng, Santa Clara, CA (US); Srinivas Vaduvatha, San Jose, CA (US); Hugh McEvoy Walsh, Los Gatos, CA (US); Prashant R. Chandra, San Jose, CA (US); Abhishek Agarwal, Santa Clara, CA (US); Weihuang Wang, Los Gatos, CA (US); and Weiwei Jiang, Santa Clara, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Feb. 21, 2024, as Appl. No. 18/583,341.
Application 18/583,341 is a continuation of application No. 17/834,018, filed on Jun. 7, 2022, granted, now 11,995,000.
Prior Publication US 2024/0193093 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0895 (2016.01); G06F 12/0864 (2016.01); G06F 12/121 (2016.01)
CPC G06F 12/0895 (2013.01) [G06F 12/0864 (2013.01); G06F 12/121 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A packet cache system comprising:
a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address;
a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value;
a cache memory for storing the packet at a location indicated by the cache memory address;
an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high; and
a reorder engine for receiving a read request comprising a read address corresponding to the non-cache memory and allocated to a desired packet to be read from either the cache memory or the non-cache memory, and for storing the desired packet, upon reading from either the cache memory or the non-cache memory, into a reorder buffer such that the desired packet is supplied in response to the read request at a timing proper relative to a timing of other read requests.