US 12,216,585 B2
Coherent memory access
Timothy P. Finkbeiner, Boise, ID (US); and Troy D. Larsen, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Mar. 31, 2023, as Appl. No. 18/129,559.
Application 18/129,559 is a continuation of application No. 17/843,387, filed on Jun. 17, 2022, granted, now 11,620,228.
Application 17/843,387 is a continuation of application No. 17/013,313, filed on Sep. 4, 2020, granted, now 11,397,688, issued on Jul. 26, 2022.
Application 17/013,313 is a continuation of application No. 16/156,654, filed on Oct. 10, 2018, granted, now 10,769,071, issued on Sep. 8, 2020.
Prior Publication US 2024/0296124 A1, Sep. 5, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/0877 (2016.01)
CPC G06F 12/0877 (2013.01) [G06F 2212/221 (2013.01); G06F 2212/656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first cache line and a second cache line coupled to a memory array;
a first cache controller coupled to a first processing resource and to the first cache line and configured to provide coherent access to data stored in the second cache line and corresponding to a memory address; and
a second cache controller coupled through an interface to a second processing resource and coupled to the second cache line and configured to provide coherent access to data stored in the first cache line and corresponding to the memory address,
wherein coherent access is provided by, responsive to determining that the memory address is stored in a cache line address register of the first cache controller, locking the first cache line prior to copying the data from the first cache line to the second cache line.