US 12,216,581 B2
System, method, and apparatus for enhanced pointer identification and prefetching
Sreenivas Subramoney, Bangalore (IN); Stanislav Shwartsman, Haifa (IN); Anant Nori, Bangalore (IN); Shankar Balachandran, Bangalore (IN); Elad Shtiegmann, Kefar Sava (IL); Vineeth Mekkat, San Jose, CA (US); Manjunath Shevgoor, San Jose, CA (US); and Sourabh Alurkar, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 19, 2023, as Appl. No. 18/320,780.
Application 18/320,780 is a continuation of application No. 17/391,962, filed on Aug. 2, 2021, granted, now 11,693,780.
Application 17/391,962 is a continuation of application No. 16/234,135, filed on Dec. 27, 2018, granted, now 11,080,194, issued on Aug. 3, 2021.
Prior Publication US 2023/0409481 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 2212/602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
predictor circuitry to detect a pointer load instruction to load a pointer based, at least in part, on one or more previously executed pointer load instructions, wherein the one or more previously executed pointer load instructions caused access to a second memory address satisfying a condition relative to a first memory address identified by the pointer load instruction; and
prefetcher circuitry to detect an upcoming execution of the pointer load instruction and to prefetch the pointer at the first memory address and data for a next data load instruction, the next data load instruction associated with the pointer load instruction, wherein a location of the data is identified based on the pointer.