US 12,216,580 B1
Peripheral device with cache updating from multiple sources
Yaniv Strassberg, Yokneam (IL); Guy Harel, Haifa (IL); Gabi Liron, Yokneam Illit (IL); and Yuval Itkin, Zoran (IL)
Assigned to Mellanox Technologies, Ltd., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Aug. 28, 2023, as Appl. No. 18/456,536.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 12/084 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/0815 (2013.01) [G06F 12/084 (2013.01); G06F 12/1408 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A peripheral device, comprising:
a processor, to execute software code;
a cache memory, to cache a portion of the software code;
memory interface, to communicate with a non-volatile memory (NVM) that stores a replica of the software code;
a host interface, to communicate over a peripheral bus with one or more hosts that store additional respective replicas of the software code; and
a cache controller, to:
determine for each of the one or more hosts, whether the host is to be allocated or not for code fetching, based on a specified allocation criterion;
receive a request from the processor for a segment of the software code;
when the segment is available in the cache memory, fetch the segment from the cache memory;
when the segment is unavailable in the cache memory and at least one of the hosts is allocated, fetch the segment from the at least one of the hosts that are allocated, via the host interface;
when the segment is unavailable in the cache memory and none of the one or more hosts is allocated, fetch the segment from the NVM via the memory interface; and
serve the fetched segment to the processor.