US 12,216,576 B2
Method and apparatus to reduce cache stampeding
Raikirat Sohi, Sunnyvale, CA (US); Mayur Saxena, San Jose, CA (US); and Sandeep Singh, Sunnyvale, CA (US)
Assigned to Walmart Apollo, LLC, Bentonville, AR (US)
Filed by Walmart Apollo, LLC, Bentonville, AR (US)
Filed on Aug. 3, 2022, as Appl. No. 17/880,481.
Claims priority of provisional application 63/229,224, filed on Aug. 4, 2021.
Prior Publication US 2023/0046354 A1, Feb. 16, 2023
Int. Cl. G06F 12/0802 (2016.01); G06F 12/121 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 12/121 (2013.01); G06F 2212/60 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus configured to at least reduce cache stampeding, the apparatus comprising:
a memory having a data cache stored therein; and
a control circuit operably coupled to the memory and configured as a probabilistic data structure to update the data cache in accordance with a scheduled update time, by:
prior to the scheduled update time, computing selected entries of the data cache pursuant to a prioritization scheme that uses hash functions to map events to frequencies using sub-linear space, the prioritization scheme creating a score for entries of the data cache that comprises a normalized function of a use frequency of the entry added with a random value generated using a jitter function;
generating a substitute data cache using the computed selected entries; and
at the scheduled update time, switching the substitute data cache for the data cache such that data queries made subsequent to the scheduled update time access the substitute data cache and not the data cache.