US 12,216,566 B2
Debug operations on artificial intelligence operations
Alberto Troia, Munich (DE)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Sep. 26, 2022, as Appl. No. 17/953,130.
Application 17/953,130 is a continuation of application No. 16/553,897, filed on Aug. 28, 2019, granted, now 11,455,232.
Prior Publication US 2023/0015438 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/36 (2006.01); G06F 13/16 (2006.01); G06N 3/04 (2023.01)
CPC G06F 11/364 (2013.01) [G06F 11/0778 (2013.01); G06F 11/0787 (2013.01); G06F 13/1668 (2013.01); G06N 3/04 (2013.01)] 19 Claims
OG exemplary drawing
 
6. An apparatus, comprising:
an artificial intelligence (AI) accelerator;
a number of memory arrays coupled to the AI accelerator;
a number of registers coupled to the AI accelerator; and
a controller coupled to the AI accelerator, wherein the controller is configured to:
perform an AI operation via the AI accelerator using at least one of: activation function data, partial results of AI operations, or bias value data;
store a location of a layer of a neural network where an error occurred during the AI operation in a first register of the number of registers in response to the error occurring;
stop the AI operation at the layer of the neural network where the error occurred;
perform a debug operation on the AI operation to identify errors of the AI operation in response to a particular bit of a second register of the number of registers being programmed to a particular state;
store data in a temporary memory block of the number of memory arrays in response to a particular bit of a third register of the number of registers being programmed to a particular state; and
change the data stored in the temporary memory block to correct the identified errors.