CPC G06F 11/27 (2013.01) [G06F 12/0238 (2013.01); G06F 2212/202 (2013.01)] | 19 Claims |
1. A multiple-name-space testing system comprising:
a load board configured to couple with a plurality of devices under test (DUTs);
test electronics configured to test the plurality of DUTs, wherein the test electronics are coupled to the load board; and
a controller configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel, wherein the multiple-name-spaces are located in the plurality of DUTs and wherein the controller is coupled to the testing electronics, wherein the controller handles user introduced testing requirements, and wherein the user introduced testing requirements comprise indicating that a first namespace is to be tested with full field programmable gate array (FPGA) hardware acceleration and indicating a second namespace is to be tested normally, wherein the controller comprises a namespace testing tracker configured to participate in namespace tracking and testing management of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel, wherein the namespace tracking and testing management comprises consideration of namespace characteristics and test equipment features, wherein the namespace characteristics comprise sizes of memory associated with the multiple-name-spaces and the test equipment features comprise hardware acceleration features and normal testing features.
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