US 12,216,543 B2
Fault tolerant memory systems and components with interconnected and redundant data interfaces
Kenneth L. Wright, Sunnyvale, CA (US); and Frederick A. Ware, Los Altos Hills, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on May 30, 2023, as Appl. No. 18/203,576.
Application 18/203,576 is a continuation of application No. 17/354,268, filed on Jun. 22, 2021, granted, now 11,709,736.
Application 17/354,268 is a continuation of application No. 16/290,759, filed on Mar. 1, 2019, granted, now 11,061,773, issued on Jul. 13, 2021.
Application 16/290,759 is a continuation of application No. 15/260,880, filed on Sep. 9, 2016, granted, now 10,235,242, issued on Mar. 19, 2019.
Claims priority of provisional application 62/233,550, filed on Sep. 28, 2015.
Prior Publication US 2023/0359526 A1, Nov. 9, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 3/06 (2006.01); G06F 11/14 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01)
CPC G06F 11/142 (2013.01) [G06F 3/0617 (2013.01); G06F 3/0634 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 11/00 (2013.01); G06F 13/1673 (2013.01); G06F 13/4068 (2013.01); H01L 24/00 (2013.01); H01L 24/17 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); G06F 11/1423 (2013.01); G06F 2201/805 (2013.01); G06F 2201/82 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32014 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/4824 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory module comprising:
a printed-circuit board with a module connector, the module connector having:
a first module data connection; and
a second module data connection;
a first memory component mounted to the printed-circuit board and having:
first memory;
a first data interface connected to the first module data connection, the first data interface to communicate between the first module data connection and the first memory; and
a second data interface to communicate with the first memory;
a second memory component mounted to the printed-circuit board and having:
second memory;
a third data interface connected to the second module data connection, the third data interface to communicate between the second module data connection and the second memory; and
a fourth data interface connected to the second data interface, the fourth data interface to communicate between the second data interface and the second memory; and
a mode register to store a mode value disabling the first data interface from communicating with the first module data connection.