| CPC G06F 11/1068 (2013.01) [G06F 11/0784 (2013.01); G06F 11/1004 (2013.01)] | 16 Claims |
|
11. A method for correcting an aligned error performed by a semiconductor system including a memory chip including a first memory, and a control chip including an Error Correction Code (ECC) circuit for controlling the memory chip, comprising:
obtaining target data to be encoded, and encoding the target data by multiplying a generator matrix of an ECC which was generated previously;
storing the encoded target data in the first memory of the memory chip;
reading the encoded target data from the first memory of the memory chip or reading transformed transmission data which was transformed during transmission; and
generating an error corrected data by correcting single errors of the transformed transmission data and a plurality of double adjacent errors that does not exceed a first value boundary of a predetermined number of bits by using a parity check matrix of the ECC and outputting the error corrected data.
|