US 12,216,539 B2
Page retirement techniques for multi-page DRAM faults
Sudhanva Gurumurthi, Austin, TX (US); Vilas Sridharan, Boston, MA (US); and Majed Valad Beigi, Burlington, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Oct. 31, 2022, as Appl. No. 17/977,001.
Prior Publication US 2024/0143440 A1, May 2, 2024
Int. Cl. G06F 11/30 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 12/1027 (2016.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0793 (2013.01); G06F 12/1027 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
scrubbing a set of adjacent pages of a dynamic random access memory (DRAM) based on a miss at a translation lookaside buffer (TLB) of a page of the set; and
in response to detecting an uncorrectable error at a first page of the set, retiring a second page of the set.