US 12,216,537 B2
Error detection, prediction and handling techniques for system-in-package memory architectures
Dimin Niu, Sunnyvale, CA (US); Tianchan Guan, Shanghai (CN); Hongzhong Zheng, Los Gatos, CA (US); and Shuangchen Li, Sunnyvale, CA (US)
Assigned to Alibaba Group Holding Limited, Grand Cayman (KY)
Appl. No. 18/035,498
Filed by Alibaba Group Holding Limited, Grand Cayman (KY)
PCT Filed Nov. 4, 2020, PCT No. PCT/CN2020/126346
§ 371(c)(1), (2) Date May 4, 2023,
PCT Pub. No. WO2022/094776, PCT Pub. Date May 12, 2022.
Prior Publication US 2024/0020194 A1, Jan. 18, 2024
Int. Cl. G06F 11/10 (2006.01); G11C 7/04 (2006.01)
CPC G06F 11/1044 (2013.01) [G11C 7/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system-in-package (SiP) comprising:
one or more memory dice including:
a memory array arranged in a plurality of blocks;
an electronic fuse (eFuse) module configured to store memory health information of the one or more memory dice; and
a memory error correcting code (ECC) flag register configured to store on-die memory error information of the one or more memory dice; and
a logic die including:
computation logic;
a memory controller configured to communicatively couple the computation logic to the one or more memory dice, wherein the memory controller includes a system error correcting code (ECC) flag register configured to store system memory error information and a read address buffer configured to store memory read addresses; and
a reliability availability serviceability (RAS) memory management unit (MMU) configured to communicatively couple the memory controller to a host, wherein the RAS MMU is configured to manage memory error detection, memory error prediction and memory error handling based on the eFuse module, the memory error correcting code (ECC) flag register, the system error correcting code (ECC) flag register and the read address buffer.