| CPC G06F 11/1004 (2013.01) [G06F 11/0772 (2013.01); G06F 11/3031 (2013.01); G06F 13/4291 (2013.01)] | 20 Claims |

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1. A device comprising:
an integrated circuit; and
a serial peripheral interface (SPI) communicatively coupled to the integrated circuit,
wherein the SPI comprises a Master In Slave Out (MISO) channel and a Master Out Slave In (MOSI) channel, and
wherein the integrated circuit is configured to:
provide, to the MOSI channel, a write address within a subcontroller to be written to;
provide, to the MOSI channel, payload data to be written;
provide, to the MOSI channel, a forward error-checking code usable to identify data corruption within the write address or the payload data;
receive, from the MISO channel, a reverse error-checking code calculated by the subcontroller based on the write address and the payload data, wherein the reverse error-checking code is usable to identify data corruption within the write address or the payload data;
compare the reverse error-checking code to the forward error-checking code to determine that a transmission error has occurred; and
initiate, in response to determining that the transmission error has occurred, appropriate remedial action.
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