US 12,216,529 B2
Adaptive frequency control for high-speed memory devices
Jian Huang, Union City, CA (US); Zhenming Zhou, San Jose, CA (US); Zhongguang Xu, San Jose, CA (US); and Murong Lang, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 19, 2022, as Appl. No. 17/933,443.
Application 17/933,443 is a continuation of application No. 16/996,267, filed on Aug. 18, 2020, granted, now 11,449,377.
Prior Publication US 2023/0011150 A1, Jan. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G06F 11/076 (2013.01) [G06F 11/0727 (2013.01); G06F 11/1068 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
operating both a memory controller and a memory die simultaneously at an initial operating frequency during a read operation;
detecting an occurrence of an error event during the read operation;
setting an error threshold criterion;
determining, with respect to the initial operating frequency, an adjusted value for a current operating frequency of at least one of the memory controller and the memory die;
determining whether the adjusted value of the current operating frequency satisfies the error threshold criterion;
responsive the determining that the adjusted value of the current operating frequency satisfies the error threshold criterion, updating the operating frequency of the at least one of the memory controller or the memory die to the adjusted value of the current operating frequency; and
responsive the determining that the adjusted value of the current operating frequency does not satisfy the error threshold criterion, continuing to operate the memory controller and a memory die at the initial frequency.