| CPC G06F 1/12 (2013.01) [G06F 1/08 (2013.01); G06F 1/14 (2013.01)] | 22 Claims |
|
1. A clock synchronization system, comprising:
clock circuitry to maintain a clock running at a clock frequency;
a clock controller; and
a processor to execute software to generate clock update commands and provide the clock update commands to the clock controller, wherein the clock controller is configured to:
apply the clock update commands to the clock;
store a holdover frequency command to maintain the clock during a failure of the clock update commands;
apply the holdover frequency command to the clock responsively to detecting the failure, wherein the clock controller or the software is configured to generate the holdover frequency command responsively to any one or more of the following: an average of clock updates; a mean of clock updates; a median of clock updates; and a mode of clock updates; and
apply the holdover frequency command to the clock in the absence of the clock controller receiving any clock update command within a time period derived from timing criteria.
|