| CPC G06F 1/04 (2013.01) [H03K 19/20 (2013.01)] | 21 Claims |
|
1. A system comprising:
a clockless trigger circuit comprising a first-state asynchronous event input to receive a first-state asynchronous event signal, and a second-state asynchronous event input to receive a second-state asynchronous event signal, wherein the clockless trigger circuit is configured to:
assert a first trigger signal in response to the first-state asynchronous event signal being asserted while an asynchronous finite state machine is in a first state; and
assert a second trigger signal in response to the second-state asynchronous event signal being asserted while the asynchronous finite state machine is in a second state;
a clockless virtual clock-pulse circuit coupled to the clockless trigger circuit, and configured to:
receive the first trigger signal and generate a first virtual-clock event in response to the first trigger signal being asserted; and
receive the second trigger signal and generate a second virtual-clock event in response to the second trigger signal being asserted; and
the asynchronous finite state machine, coupled to the clockless trigger circuit and the clockless virtual clock-pulse circuit, and configured to:
generate a retimed first-state asynchronous event signal in response to receiving the first-state asynchronous event signal and the first virtual-clock event;
transition from the first state to the second state in response to the retimed first-state asynchronous event signal and to the first virtual-clock event; and
generate a retimed second-state asynchronous event signal in response to receiving the second-state asynchronous event signal and the second virtual-clock event; and
transition from the second state to a third state in response to the retimed second-state asynchronous event signal and to the second virtual-clock event.
|