US 12,216,382 B1
Processor circuit for generating ultrafast clock multiplier
Bicky A. Marquez, Kingston (CA)
Assigned to Milkshake Technology Inc., Menlo Park, CA (US)
Filed by Milkshake Technology Inc., Menlo Park, CA (US)
Filed on Jan. 11, 2024, as Appl. No. 18/410,910.
Int. Cl. G02F 3/02 (2006.01); G02B 6/12 (2006.01); G02F 1/01 (2006.01); G06F 1/04 (2006.01); H01S 3/00 (2006.01); H03K 3/86 (2006.01)
CPC G02F 3/028 (2013.01) [G02B 6/12004 (2013.01); G02F 1/0126 (2013.01); G06F 1/04 (2013.01); H01S 3/0057 (2013.01); H03K 3/86 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A photonic circuit, comprising:
a beam splitter having at least one input to receive a photonic seed clock signal, the beam splitter configured to split the photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal;
a phase shifter having at least one input to receive a photonic signal, the phase shifter configured to shift a phase of the received photonic signal to generate a phase-shifted version of the photonic signal;
a first photonic combiner having a first set of one or more inputs, a first input of the first set of one or more inputs coupled to a first output of the beam splitter, a second input of the first set of one or more inputs coupled to an output of the phase shifter, the first photonic combiner configured to combine the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal; and
a second photonic combiner having a second set of one or more inputs, a first input of the second set of one or more inputs coupled to a second output of the beam splitter, a second input of the second set of one or more inputs coupled to an output of the first photonic combiner, the second photonic combiner configured to combine a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.